cystech electronics corp. spec. no. : c654t3 issued date : 2010.09.21 revised date : page no. : 1/6 BTD2195T3 cystek product specification npn epitaxial planar transistor bv ceo 120v i c 4a v ce(sat) BTD2195T3 1.5v(max) description the BTD2195T3 is designed for use in general pur pose amplifier and low speed switching application. pb-free lead plating pack age process is adopted. equivalent circuit outline absolute maximum ratings (ta=25 c) BTD2195T3 to-126 c b r 2 P120 e r 1 P8k b base c collector e emitter e c b parameter symbol limits unit collector-base voltage v cbo 130 collector-emitter voltage v ceo 120 v ebo 5 v emitter-base voltage collector current (dc) i c 4 collector current (pulse) i cp 6 (note 1) a t a =25 c 1.25 power dissipation p d 40 w t c =25 c thermal resistance, junction to ambient r ja 100 r jc 3.13 c/w thermal resistance, junction to case operating junction temperature range tj -55~+150 c storage temperature range tstg -55~+150 note : 1. single pulse pw Q 300 s, duty Q 2%.
cystech electronics corp. spec. no. : c654t3 issued date : 2010.09.21 revised date : page no. : 2/6 BTD2195T3 cystek product specification characteristics (ta=25 c) symbol min. typ. max. unit test conditions bv ceo 120 - - v i c =1ma, i b =0 bv cbo 130 - - v i c =100 a, i e =0 i cbo - - 10 a v cb =100v, i e =0 i ceo - - 10 a v ce =100v, i b =0 i ebo - - 2 ma v eb =5v, i c =0 *v ce(sat) - - 1.5 v i c =2a, i b =2ma *v be(on) 2 v v ce =4v, i c =2a *h fe 1 1000 - - - v ce =4v, i c =1a *h fe 2 1000 - - - v ce =4v, i c =2a cob - 200 pf v cb =10v, i e =0a, f=1mhz *pulse test : pulse width 380 s, duty cycle 2% ordering information device package shipping marking BTD2195T3 to-126 (pb-free lead plating) 200 pcs / bag, 15 bags/box, 10 boxes/carton d2195
cystech electronics corp. spec. no. : c654t3 issued date : 2010.09.21 revised date : page no. : 3/6 BTD2195T3 cystek product specification typical characteristics current gain vs collector current 10 100 1000 10000 100000 1 10 100 1000 10000 collector current---ic(ma) current gain---hfe ta=25c ta=75c ta=125c vce=3v current gain vs collector current 10 100 1000 10000 100000 1 10 100 1000 10000 collector current---ic(ma) current gain---hfe ta=25c ta=75c ta=125c vce=4v saturation voltage vs collector current 100 1000 10000 10 100 1000 10000 collector current---ic(ma) saturation voltage---(mv) ta@125 ta=75c vcesat@ic=250ib ta=25c saturation voltage vs collector current 100 1000 10000 10 100 1000 10000 collector current---ic(ma) saturation voltage---(mv) ta@125 ta=75c vcesat@ic=500ib ta=25c saturation voltage vs collector current 100 1000 10000 10 100 1000 10000 collector current---ic(ma) saturation voltage---(mv) ta=125c vbesat@ic=250ib ta=25c 75c saturation voltage vs collector current 100 1000 10000 10 100 1000 10000 collector current---ic(ma) saturation voltage---(mv) ta=125c vbesat@ic=250ib ta=25c 75c
cystech electronics corp. spec. no. : c654t3 issued date : 2010.09.21 revised date : page no. : 4/6 BTD2195T3 cystek product specification typical characteristics(cont.) on voltage vs collector current 100 1000 10000 1 10 100 1000 10000 collector current---ic(ma) on voltage---(mv) ta=125c vbeon@vce=4v ta=25c 75c built-in diode characteristics 100 1000 10000 1 10 100 1000 10000 forward current---if(ma) forward voltage---vf(mv) ta=125c ta=25c 75c power derating curve 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 50 100 150 200 ambient temperature---ta() power dissipation---pd(w) power derating curve 0 5 10 15 20 25 30 35 40 45 0 50 100 150 200 case temeprature---tc() power dissipation---pd(w)
cystech electronics corp. spec. no. : c654t3 issued date : 2010.09.21 revised date : page no. : 5/6 BTD2195T3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 5 +1/-1 seconds 260 +0/-5 c recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds ? time(ts min to ts max ) time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
cystech electronics corp. spec. no. : c654t3 issued date : 2010.09.21 revised date : page no. : 6/6 BTD2195T3 cystek product specification to-126 dimension *: typical inches millimeters inches a b c f d e h 1 2 3 k j i 3 4 l m 1 2 g marking: d2195 device name date code style: pin 1.emitter 2.collector 3.base 3-lead to-126 plastic package cystek packa g e code: t3 millimeters dim min. max. min. max. dim min. max. min. max. 1 - *3 - *3 f 0.0280 0.0319 0.71 0.81 2 - *3 - *3 g 0.0480 0.0520 1.22 1.32 3 - *3 - *3 h 0.1709 0.1890 4.34 4.80 4 - *3 - *3 i 0.0950 0.1050 2.41 2.66 a 0.1500 0.1539 3.81 3.91 j 0.0450 0.0550 1.14 1.39 b 0.2752 0.2791 6.99 7.09 k 0.0450 0.0550 1.14 1.39 c 0.5315 0.6102 13.50 15.50 l - *0.0217 - *0.55 d 0.2854 0.3039 7.52 7.72 m 0.1378 0.1520 3.50 3.86 e 0.0374 0.0413 0.95 1.05 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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